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copyright ?2000 alliance semiconductor. all rights reserved. ? AS4C1M16F5 6/1/00 alliance semiconductor 1 5v 1m16 cmos dram (fast-page mode) features ? organization: 1,048,576 words 16 bits ?high speed - 50/60 ns ras access time - 20/25 ns fast page cycle time - 13/17 ns cas access time ? low power consumption - active: 880 mw max (as4c1m16e0-60) - standby: 11 mw max, cmos dq ? fast page mode ? 1024 refresh cycles, 16 ms refresh interval - ras -only or cas -before- ras refresh ? read-modify-write ? ttl-compatible, three-state dq ? jedec standard package and pinout - 400 mil, 42-pin soj - 400 mil, 44/50-pin tsop ii ? 5v power supply ? industrial and commercial temperature available pin arrangement 42 41 40 39 38 37 36 35 34 33 v ss dq16 dq15 dq14 dq13 v ss dq12 dq11 dq10 dq9 soj 32 31 30 29 28 27 26 25 24 23 nc lcas ucas oe a9 a8 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 vcc dq1 dq2 dq3 dq4 vcc dq5 dq6 dq7 dq8 11 12 13 14 15 16 17 18 19 20 nc nc we ras nc nc a0 a1 a2 a3 22 21 vcc a7 v cc dq1 dq2 dq 3 dq4 v cc dq5 dq6 dq7 dq8 nc nc v ss dq16 dq15 dq14 dq13 v ss dq12 dq11 dq10 dq9 nc nc lcas ucas oe 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 tsop ii 23 24 25 28 27 26 nc we ras nc nc a0 a1 a2 a3 v cc a9 a8 a7 a6 a5 a4 v ss pin designation pin(s) description a0 to a9 address inputs ras row address strobe dq1 to dq16 input/output oe output enable we write enable ucas column address strobe, upper byte lcas column address strobe, lower byte v cc power v ss ground selection guide symbol AS4C1M16F5-50 AS4C1M16F5-60 unit maximum ras access time t rac 50 60 ns maximum column address access time t aa 25 30 ns maximum cas access time t cac 13 17 ns maximum output enable ( oe ) access time t oea 13 15 ns minimum read or write cycle time t rc 84 104 ns minimum fast page mode cycle time t pc 20 25 ns maximum operating current i cc1 170 160 ma maximum cmos standby current i cc5 2.0 2.0 ma
? 2 alliance semiconductor 6/1/00 AS4C1M16F5 functional description the AS4C1M16F5 is a high performance 16-megabit cmos dynamic random access memory (dram) organized as 1,048,576 words 16 bits. the AS4C1M16F5 is fabricated using advanced cmos technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. the alliance 16mb dram family is optimized for use as main memory in personal and portable pcs, workstations, and multimedia and router switch applications. the AS4C1M16F5 features high speed page mode operation where read and write operations within a single row (or page) can be executed at very high speed (15 ns from xcas )by toggling column addresses within that row. row and column addresses are alternately latched into input buffers using the falling edge of ras and xcas inputs respectively. also, ras is used to make the column address latch transparent, enabling application of column addresses prior to xcas assertion. the AS4C1M16F5 provides dual ucas and lcas for independent byte control of read and write access. refresh on the 1024 address combinations of a0 to a9 must be performed every 16 ms using: ? ras -only refresh: ras is asserted while xcas is held high. each of the 1024 rows must be strobed. outputs remain high impedence. ? hidden refresh: xcas is held low while ras is toggled. outputs remain low impedence with previous valid data. ? cas -before- ras refresh (cbr): at least one xcas is asserted prior to ras . refresh address is generated internally. outputs are high-impedence ( oe and we are don't care). ? normal read or write cycles refresh the row being accessed. the AS4C1M16F5 is available in the standard 42-pin plastic soj and the 44/50-pin tsop ii packages, respectively. it operates with a single power supply of 5v 0.5v. the device provides ttl compatible inputs and outputs. logic block diagram recommended operating conditions ? v il min -3.0v for pulse widths less than 5 ns. recommended operating conditions apply throughout this document unl esss otherwise spe cified. parameter symbol min nominal max unit supply voltage AS4C1M16F5 v cc 4.5 5.0 5.5 v gnd 0.0 0.0 0.0 v input voltage AS4C1M16F5 v ih 2.4 C v cc v v il C0.5 ? C0.8v ambient operating temperature commercial t a 0C70 c industrial -40 C 85 ras clock generator refresh controller 1024 1024 16 array (16,777,216) sense amp a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd address buffers a8 row decoder column decoder substrate bias generator data dq buffers oe ras ucas we clock generator we lcas dq1 to dq16 cas clock generator a9
? AS4C1M16F5 6/1/00 alliance semiconductor 3 absolute maximum ratings dc electrical characteristics parameter symbol min max unit input voltage v in -1.0 +7.0 v input voltage (dqs) v dq -1.0 v cc + 0.5 v power supply voltage v cc -1.0 +7.0 v storage temperature (plastic) t stg -55 +150 c soldering temperature time t solder C 260 10 o c sec power dissipation p d C1w short circuit output current i out C50ma parameter symbol test conditions -50 -60 unit notes minmaxminmax input leakage current i il 0v v in +5.5v, pins not under test = 0v -5 +5 -5 +5 a output leakage current i ol d out disabled, 0v v out +5.5v -5 +5 -5 +5 a operating power supply current i cc1 ras , ucas , lcas , address cycling; t rc =min C170C160ma1,2 ttl standby power supply current i cc2 ras = ucas = lcas 3 v ih C2.5C2.5ma average power supply current, ras refresh mode or cbr i cc3 ras cycling, ucas = lcas 3 v ih , t rc = min of ras low after xcas low. C170C160ma 1 fast page mode average power supply current i cc4 ras = v il , ucas or lcas, address cycling: t pc = min C120C110ma1, 2 cmos standby power supply current i cc5 ras = ucas = lcas = v cc - 0.2v C 2.0 C 2.0 ma output voltage v oh i out = -5.0 ma 2.4 C 2.4 C v v ol i out = 4.2 ma C 0.4 C 0.4 v cas before ras refresh current icc6 ras , ucas or lcas cycling, t rc = min C 170 C 160 ma
? 4 alliance semiconductor 6/1/00 AS4C1M16F5 ac parameters common to all waveforms read cycle symbol parameter -50 -60 unit notes min max min max t rc random read or write cycle time 84 C 104 C ns t rp ras precharge time 30 C 40 C ns t ras ras pulse width 50 10k 60 10k ns t cas cas pulse width 8 10k 10 10k ns t rcd ras to cas delay time 15 35 15 43 ns 6 t rad ras to column address delay time 12 25 12 30 ns 7 t rsh cas to ras hold time 10 C 10 C ns t csh ras to cas hold time 40 C 50 C ns t crp cas to ras precharge time 5 C 5 C ns t asr row address setup time 0 C 0 C ns t rah row address hold time 8 C 10 C ns t t transition time (rise and fall) 1 50 1 50 ns 4,5 t ref refresh period C 16 C 16 ms 3 t cp cas precharge time 8 C 10 C ns t ral column address to ras lead time 25 C 30 C ns t asc column address setup time 0 C 0 C ns t cah column address hold time 8 10 C ns symbol parameter -50 -60 unit notes min max min max t rac access time from ras C50C60ns6 t cac access time from cas C 13 C 17 ns 6,13 t aa access time from address C 25 C 30 ns 7,13 t rcs read command setup time 0 C 0 C ns t rch read command hold time to cas 0C0Cns9 trrh read command hold time to ras 0C0Cns9
? AS4C1M16F5 6/1/00 alliance semiconductor 5 write cycle read-modify-write cycle refresh cycle symbol parameter -50 -60 unit notes min max min max t wcs write command setup time 0 C 0 C ns 11 t wch write command hold time 10 C 10 C ns 11 t wp write command pulse width 10 C 10 C ns t rw l write command to ras lead time 10 C 10 C ns t cwl write command to cas lead time 8 C 10 C ns t ds data-in setup time 0 C 0 C ns 12 t dh data-in hold time 8 C 10 C ns 12 symbol parameter -50 -60 unit notes min max min max t rw c read-write cycle time 113 C 135 C ns t rw d ras to we delay time 67 C 77 C ns 11 t cwd cas to we delay time 32 C 35 C ns 11 t aw d column address to we delay time 42 C 47 C ns 11 symbol parameter -50 -60 unit notes min max min max t csr cas setup time ( cas -before- ras )5C5Cns3 t chr cas hold time ( cas -before-ras )8C10Cns3 t rpc ras precharge to cas hold time 0C0Cns t cpt cas precharge time (cbr counter test) 10 10 C ns
? 6 alliance semiconductor 6/1/00 AS4C1M16F5 fast page mode cycle output enable symbol parameter -50 -60 unit notes min max min max t cpa access time from cas precharge C 28 C 35 ns 13 t rasp ras pulse width 50 100k 60 100k ns t pc read-write cycle time 30 C 35 C ns t cp cas precharge time (fast page) 10 C 10 C ns t pcm fast page mode rmw cycle 80 C 85 C ns t crw page mode cas pulse width (rmw) 54 C 60 C ns symbol parameter -50 -60 unit notes min max min max t clz cas to output in low z 0 C 0 C ns 8 t roh ras hold time referenced to oe 8C10Cns t oea oe access time C 13 C 15 ns t oed oe to data delay 13 C 15 C ns t oez output buffer turnoff delay from oe 013015ns8 t oeh oe command hold time 10 C 10 C ns t olz oe to output in low z 0 C 0 C ns t off output buffer turn-off time 0 13 0 15 ns 8,10
? AS4C1M16F5 6/1/00 alliance semiconductor 7 notes 1i cc1 , i cc3 , and i cc4 are dependent on frequency. 2i cc1 and i cc4 depend on output loading. specified values are obtained w ith the output open. 3 an initial pause of 200 s is required after power-up followed by any 8 ras cycles before proper device operation is achieved. in the case of an internal refresh counter, a minimum of 8 cas -before-ras initialization cycles instead of 8 ras cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). 4 ac characteristics assume t t = 2 ns. all ac parameters are measured with a load equivalent to two ttl loads and 100 pf, v il (min) 3 gnd and v ih (max) v cc . 5v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 6 operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 7 operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 8 assumes three state test load (5 pf and a 380 w thevenin equivalent). 9either t rch or t rrh must be satisfied for a read cycle. 10 t off (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t off is referenced from rising edge of ras or cas , whichever occurs last. 11 t wcs , t wch , t rwd , t cwd and t aw d are not restrictive operating parameters. they are included in the datasheet as electrical characteristics only. if t ws 3 t ws (min) and t wh 3 t wh (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. if t rwd 3 t rw d (min), t cwd 3 t cwd (min) and t awd 3 t awd (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12 these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read-write cycles. 13 access time is determined by the longest of t caa or t cac or t cpa 14 t asc 3 t cp to achieve t pc (min) and t cpa (max) values. 15 these parameters are sampled and not 100% tested. 16 these characteristics apply to AS4C1M16F5 5v devices. ac test conditions key to switching waveforms - access times are measured with output reference levels of v oh = 2.4v and v ol = 0.4v, v ih = 2.4v and v il = 0.8v - input rise and fall times: 2 ns 100 pf* r2 = 295 w r1 = 828 w d out gnd +5v figure a: equivalent output load *including scope and jig capacitance undefined output/don?t care falling input rising input
? 8 alliance semiconductor 6/1/00 AS4C1M16F5 read waveform upper byte read waveform t ras t rc t rp t rsh t rad t rch t roh t cac t oea t off (see note 11) t oez ras ucas , address we oe dq column address t crp t csh t rcd t asc t cah t cas t ral t rah t rcs t aa t clz t rrh data out t rac t asr lcas row address t roh t wez t olz t rez t ras t rc t rp t crp t rcd t rsh t csh t crp t crp t asr t rah t rad t ral t cah t rcs t rrh t rch t clz t cac t off row data out ras ucas lcas address we oe upper dq lower dq t roh t asc t rac t oea t aa t cas t oez column t rez t wez t olz t rpc
? AS4C1M16F5 6/1/00 alliance semiconductor 9 lower byte read waveform early write waveform t ras t rc t rp t rcd t rsh t crp t asr t rah t rad t ral t cah t rrh t rch t clz t cac t rac t off data out ras lcas ucas address we oe upper dq lower dq t csh t asc t rcs t roh t oea t aa t cas t crp t crp row t oez column t olz t rez t wez t rpc t ras t rc t rp t crp t rsh t rcd t csh t cas t rad t asc t cah t wcs t cwl t rwl t wch t wp t ds t dh data in ras ucas , address we oe dq row address t ral column address t rah t asr lcas
? 10 alliance semiconductor 6/1/00 AS4C1M16F5 upper byte early write waveform lower byte early write waveform t ras t rc t rp t rah t rad t asc t cah t rsh t rcd t csh t crp t rpc t rw l t wcs t wp t ds t dh column address data in ras address ucas lcas we oe upper dq lower dq t asr t ral t cwl row address t crp t crp t wch t cas t rc t ras t rp t rad t crp t rpc t crp t asc t cah t rsh t rcd t csh t rwl t wp t wcs t wch t ds t dh row address column address data in ras address ucas lcas we oe upper dq lower dq t cwl t rah t cas t asr t ral t crp
? AS4C1M16F5 6/1/00 alliance semiconductor 11 write waveform oe controlled upper byte write waveform oe controlled row address t ras t rc t rp t crp t rsh t rcd t csh t cas t rah t ral t rad t cah t cwl t rw l t oeh t ds t dh data in ras ucas , address we oe dq column address t wp t asc t asr lcas t oed t ras t rc t rp t ral t rad t asc t cah t csh t crp t crp t rpc t rw l t wp t oeh t ds t dh t oed row address column address data in ras address ucas lcas we oe upper dq lower dq t crp t rah t rcd t cas t rsh t cwl t asr
? 12 alliance semiconductor 6/1/00 AS4C1M16F5 lower byte write waveform oe controlled read-modify-write waveform t rc t ras t rp t rah t rad t ac s t cah t rsh t csh t crp t crp t rpc t rw l t wp t oeh t ds t dh row address column address data in ras address lcas ucas we oe upper dq lower dq t crp t rcd t cas t cwl t ral t asr t ras t rwc t rp t crp t rsh t rcd t csh t cas t rad t ral t ar t cah t cwl t cwd t rwl t awd t wp t oea t clz t cac t aa t ds t dh row address column address data in data out ras ucas , address we oe dq t rah t rw d t rcs t rac t oez t oed t asc t asr lcas t olz
? AS4C1M16F5 6/1/00 alliance semiconductor 13 upper byte read-modify-write waveform lower byte read-modify-write waveform t rwc t ras t rp t crp t rsh t rcd t csh t cas t crp t crp t rpc t ral t rad t cah t rwl t awd t wp t cwd t oea t ds t clz t aa t rac t cac t oez t oed data in data out ras ucas lcas address we oe upper input upper output lower input t acs t rw d t cwl t oed t rcs t rah t asr row column address t olz t dh lower output t rwc t ras t rp t crp t rpc t crp t rsh t rcd t csh t cas t crp t ral t rad t rcs t oea t oed t ds t clz t oez row column address data in data out ras ucas lcas address we oe upper input upper output lower input lower output t rah t awd t cwl t cwd t cac t rwd t asr t aa t rac t acs t cah t rwl t wp t dh t olz t oed
? 14 alliance semiconductor 6/1/00 AS4C1M16F5 fast page mode read waveform fast page mode byte write waveform row t rasp t rp t crp t rcd t cas t csh t rsh t pc t asr t rad t rch t rcs t rrh t rch t oea t oea t aa t rac t oez t cac data out data out data out column column column ras cas address we oe i/o t ar t rah t asc t cah t ral t rcs t clz t cp t off t cap t rasp t rp t rcd t csh t cas t cp t crp t asr t cah t cah t ral t cah t cwd t awd t cwd t cwl t cwd t awd t rw l t wp t oez t oea t rac t ds t clz t cac t cap row column column column data out data in data in data out data out data in ras cas address we oe i/o t rad t rah t rw d t rcs t cwl t oea t aa t dh t ds t clz t cac t clz t cac t oed t pcm
? AS4C1M16F5 6/1/00 alliance semiconductor 15 fast page mode early write waveform cas before ras refresh waveform we = a = v ih or v il ras only refresh waveform we = oe = v ih or v il t rasp t rw l t asc t wcs t cp t ral t wch t cwl t wp t ds t dh t cas row column column column data in data in data in ras cas address we oe i/o t pc t cah t csh t rcd t oeh t hdr t ar t rad t asr t crp t rah t rsh t oed t rp t rc t ras t rpc t cp t csr t chr ras ucas , dq lcas open t ras t rp t rc t crp t rpc t asr t rah row address ras address ucas , lcas
? 16 alliance semiconductor 6/1/00 AS4C1M16F5 hidden refresh waveform (read) hidden refresh waveform (write) t ras t rc t rp t ras t rc t rp t crp t rcd t rsh t crp t chr t asr t rad t asc t rrh t oea t clz t cac t oez col address row data out ras cas address we oe dq t ar t rah t rac t aa t rcs t cah t off t ras t rc t rp t crp t rcd t rsh t asr t rah t rad t ar t cah t wcs t wch t ds t dh data in col address row address ras ucas , address we dq oe t asc t rw l t wcr t wp t dhr t ral lcas t chr
? AS4C1M16F5 6/1/00 alliance semiconductor 17 cas before ras refresh counter test waveform t ras t rsh t rp t csr t chr t cpt t cas t cah t clz t cac t rch t rrh t roh t oea t rw l t cwl t wcs t wp t wch t ds t dh t rcs t oea t ds t dh col address data out data in data out data in ras ucas , address dq we oe we dq oe we oe dq t oed t aa t clz t cac t oez t wp t cwl t rcs t aa t oez t awd t cwd t ral read cycle write cycle read-write cycle lcas t asc t off t rwl
? 18 alliance semiconductor 6/1/00 AS4C1M16F5 package dimensions e d e1 pin 1 b b a1 a2 c e seating plane e2 a 42-pin soj 400 mil min max a 0.128 0.148 a1 0.025 - a2 0.105 0.115 b 0.026 0.032 b 0.015 0.020 c 0.007 0.013 d 1.070 1.080 e 0.370 nom e1 0.395 0.405 e2 0.435 0.445 e 0.050 nom soj 50-pin tsop ii min (mm) max (mm) a1.2 a 1 0.05 a 2 0.95 1.05 b0.300.45 c0.120.21 d 20.85 21.05 e 10.03 10.29 h e 11.56 11.96 e 0.80 (typical) l0.400.60 d h e 1234567891011 50 49 48 47 46 45 44 43 42 41 40 15 16 36 35 17 18 19 20 34 33 32 31 c l a 1 a 2 e tsop ii 0C5 21 30 22 23 24 25 29 28 27 26 e a b
? AS4C1M16F5 6/1/00 alliance semiconductor 19 typical dc and ac characteristics supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t rac ambient temperature (c) C55 80 125 35 C10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t rac load capacitance (pf) 50 200 250 150 100 30 40 60 70 50 80 90 100 typical access time typical access time t rac vs. ambient temperature t a vs. load capaci tance c l vs. supply voltage v cc t a = 25c -70 -60 -50 supply voltage (v) 4.0 5.5 6.0 5.0 4.5 100 110 130 140 120 150 160 170 supply current (ma) typical supply current i cc ambient temperature (c) C55 80 125 35 C10 100 110 130 140 120 150 160 170 supply current (ma) typical supply current i cc cycle rate (mhz) 28 10 6 4 0.0 5 15 20 10 25 30 35 power-on current (ma) typical power-on current i po vs. ambient temperature t a vs. cycle rate 1/t rc vs. supply voltage v cc -50 -60 -50 -60 supply voltage (v) 4.0 5.5 6.0 5.0 4.5 20 40 80 100 60 120 140 160 refresh current (ma) typical refresh current i cc3 ambient temperature (c) 0.0 60 80 40 20 refresh current (ma) typical refresh current i cc3 supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0 0.5 1.5 2.0 1.0 2.5 3.0 3.5 stand-by current (ma) typical ttl stand-by current i cc2 vs. ambient temperature ta vs. supply voltage v cc vs. supply voltage v cc 20 40 80 100 60 120 140 160 -50 -60 -50 -60
? 20 alliance semiconductor 6/1/00 AS4C1M16F5 capacitance 15 ? = 1 mhz, t a = room temperature AS4C1M16F5 ordering information parameter symbol signals test conditions max unit input capacitance c in1 a0 to a9 v in = 0v 5 pf c in2 ras , ucas , lcas , we , oe v in = 0v 7 pf dq capacitance c dq dq0 to dq15 v in = v out = 0v 7 pf package \ ras access time 50 ns 60 ns plastic soj, 400 mil, 42-pin 5v AS4C1M16F5-50jc AS4C1M16F5-50ji AS4C1M16F5-60jc AS4C1M16F5-60ji tsop ii, 400 mil, 44/50-pin 5v AS4C1M16F5-50tc AS4C1M16F5-50ti AS4C1M16F5-60tc AS4C1M16F5-60ti ambient temperature (c) 060 80 40 20 0.0 0.5 1.5 2.0 1.0 2.5 3.0 3.5 stand-by current (ma) typical ttl stand-by current i cc2 output voltage (v) 0.0 1.5 2.0 1.0 0.5 0.0 10 30 40 20 50 60 70 output sink current (ma) typical output sink current i ol output voltage (v) 0.0 3.0 4.0 2.0 1.0 0.0 10 30 40 20 50 60 70 output source current (ma) typical output source current i oh vs. output voltage v ol vs. output voltage v oh vs. ambient temperature t a hyper page mode current (ma) ambient temperature (c) 060 80 40 20 0.0 20 60 80 40 100 120 140 hyper page mode current (ma) typical hyper page mode current i cc4 supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0.0 20 60 80 40 100 120 140 typical hyper page mode current i cc4 vs. supply voltage v cc vs. ambient temperature t a -50 -60 -50 -60
? AS4C1M16F5 6/1/00 alliance semiconductor 21 AS4C1M16F5 part numbering system as4 c 1m16e0 Cxx x x dram prefix c = 5v cmos device number ras access time package: j = 42-pin soj 400 mil t=44/50-pin tsop ii 400 mil temperature range c=commercial, 0c to 70c i=industrial, -40c to 85c

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